LOGIC GATES
In conventional electric circuit we use electric pulses of various types which may be of sinusoidal form or any other type. In digital electronic (branch of electronics which has led to development of computers, calculators, digital watches etc). We use electric pulses which has only two values called high value or low value. One such pulse having values 5 V and 0 at different tes in shown in [Fig. 1.]. Since binary algebra is based on two digits 1 and 0, use if binary system in digits electronics seems to be logical. Now onwards we shall denote high level by 1 and low level by 0. The development of digital electronics is based upon some electrical circuits called logic gates.
Fig. 1. High (1) and low (0) signals. |
A logic gate is a circuit having one or more than one input but having one output only.
These are three basic logic gates,
- OR gate.
- AND gate.
- NOT gate.
1. OR gate (Addition)
OR gate is the electrical circuit whose output is high when one or more of its inputs are high.
i.e. output is present when one or all the inputs are present.
OR gate works as a number of switches in parallel (Fig. 2). A closed switch means a high level signal denoted by 1 while an open switch means a low level signal denoted by 0.
Let A and B denoted as inputs, then X = A + B shall be the output.
Fig. 2. Equivalent circuit for OR gate. |
Case (i) Switches S₁ and S₂ both open (A = 0, B = 0). No current will flow through the bulb (X = 0). In this case both the inputs A and B are 0 while the output X is also 0. The state is represented by first line in the truth table.
Case (ii) Switch S₁ is closed (A = 1) while S₂ is open (B = 0). Current flows through the bulb indicating that there is output in the circuit (X = 1). The state is represented by the second line in the truth table.
Case (iii) Switch S₁ is open (A = 0) and S₂ is closed (B = 1). Current flows through the circuit (X = 1). The stage is represented by the third line in the truth table.
Case (iv) Both the Switches S₁ and S₂ are closed (A = 1, B = 1). Current flows through the circuit (X = 1). The stage us represented by fourth line in the truth table.
Fig. 3. Symbolic representation. |
The circuit diagram and its symbolic representation for OR gate is shown in [Fig. 3 (i) and (ii)] respectively.
From the circuit diagram we can see that all the inputs are given to the positive terminals of the diodes D₁ and D₂ whose negative terminals are connected to earth through a 5 KΩ resistance. When the both inputs are zero (A and B connected to E), no current flows through 5 KΩ resistance. So there will be zero voltage drop across the resistance (output X = 0). When any of the input, say A is connected to 5 V (high level voltage). Diode D₁ starts conducting thus sending the current through the resistance. This gives a high level output (X = 1). Same argument holds good for A = 0, B = 1, (A connected to E and B connected to S) and for A = 1, B = 1 (A and B both connected to S).
2. AND gate (Multiplication)
AND gate is an electric circuit which gives a high output (X = 1) only when all the inputs to the gate are high. Here output is present when all inputs are present.
If when the inputs is zero, there is no output also. Thus AND gate can be visualised as an electric circuit containing a number of switches in series with each other [Fig. 4(i)]. Mathematically it is represented by the equation X = AB.
It can be seen from [Fig. 4(i)] that current will flow through the bulb (X = 1) only if both the switches S₁ and S₂ are closed (A = 1, B = 1) as shown in fourth line of truth table [Fig. 4(ii)]. If any or both of the switches are open (A = 0, B =0), there is no output (X = 0) in the circuit. These stages are represented by the first three lines of the truth tables.
Fig. 4. Equivalent circuit for AND gate. |
The circuit diagram and the symbolic representation of AND gate is shown in [Fig. 5(i) and (ii)] respectively.
From [Fig. 5(i)] it is clear that Vc = 5 V is applied to the positive terminal of each diode through a resistance of 5 kΩ. If any of the diodes A or B has its negative terminal at zero voltage (connected to E), that diode will become forward biased. So current will flow and whole of the voltage drop due to Vc will be across the resistance of 5 kΩ and there will be no voltage at the output. Now imagine A and B both connected to S. None of the two diodes is forward biased. Therefore no current flows through 5 kΩ resistance. Whole if 'Vc' will be received directly at the output. Hence, when all inputs are high (= 1) , only then the output will be high (= 1).
Fig. 5. AND gate. |
3. NOT gate (Inverter)
NOT gate is an electrical circuit which inverts the nature of signal fed to its input. Output is present when the input is absent and vice versa.
A high signal (= 1) given to the input of a NOT gate appears as a low signal (= 0) at the output and vice versa. Since this acts as inverter only, it has only one input. The circuit diagram, symbolic representation and the truth table of a NOT gate is shown in [Fig. 6(i), (ii), (iii)] respectively.
The circuit consists of a transistor (say NPN) whose emitter-base circuit can be forward biased. 'Vc' (= 5 V) is connected to the collector through a resistance of 2.2 kΩ while the output is taken across the collector and earth.
Fig. 6. NOT gate. |
When a high (= 1) input is give to NOT gate (by connecting A and S), emitter base circuit becomes forward biased thus, sending a current through the collector circuit. This current produces a voltage drop across the resistance of 2.2 kΩ in collector circuit. There is no output (X = 0). On connecting A and E (input A = 0) there is no current in the circuit. Therefore, almost all of the voltage of Vc = 5 V is received across the output (X = 1). These two stages are represented in truth table [Fig. 6(iii)].
Combination of gates
We can produce some combinations of gates by using two or more gates, already developed (NOR and NAND gates) in series with each other. The output of one will be made the input of the other. These new combinations are highly useful in the development of digital circuit.
(i) NAND gate
It consists of a combination of AND gate and NOT gate in such a way that the output of AND gate is made as the input of NOT gate. Here output is absent when all inputs are present.
The schematic representation, symbolic representation and the truth table of NAND gate is shown in [Fig. 7 (i), (ii), (iii)] respectively.
Fig. 7. NAND gate. |
It may be noted from Fig. 7(iii) that intermediate level X' (= AB) is the output of AND gate while X (= ĀB̄) is the final output of the combination.
(ii) NOR gate
It consists of a combination of a OR gate and NOT gate in such a way that the output of OR gate is made the input of NOT gate. Here output is present when all inputs are absent.
The schematic representation, symbolic representation and the truth table of a NOR gate is shown in [Fig. 8(i), (ii), (iii)] respectively.
Fig. 8. NOR gate. |
Thus, a NOR gate gives a low output (= 0) in all the cases except when all its inputs are low.
Deduction of OR ,AND and NOT gates from NAND and NOR gates
It can be shown that a repeated use of NAND and NOR and yield OR, AND and NOT gate. Therefore, NAND and NOR gates act as the basic circuits for the development of digital instruments.
(i) NOT gate from NAND gate
To obtain a NOT gate from a NAND gate we connect all the inputs of a NAND gate with each other, so that there is one output to one input. The schematic representations is shown in Fig. 9(i).
Fig. 9. NOT gate from NAND gate. |
The truth table of the combination is given in Fig. 9(ii). Comparing Fig. 9(iii) and Fig. 9(ii) it can be seen that this table represents a NOT gate.
(ii) AND gate from NAND gate
To obtain AND gate from NAND gate, the output of one NAND gate is connected to both the inputs of second NAND gate. The output of second NAND gates is the final output. The schematic representation and its truth table are shown in [Fig. 10(i) and (ii)] respectively.
Fig. 10. AND gate from NAND gate. |
Comparing Fig. 4(ii) and Fig. 10(ii), it can be seen that this truth table is same as that of AND gate.
(iii) OR gate from NAND gate
To get OR gate from NAND gate, we shall make use of three NAND gates. NAND gate N₁ has its inputs short circuited. So it acts as a NOT gate. Same is the case with NAND gate N₂ . The outputs of N₁ and N₂ are connected to the inputs of a third NAND gate N₃ whose output X is the final output. The schematic representation and its truth table is shown in [Fig. 11(i) and (ii)] respectively.
Fig. 11. OR gate from NAND gate. |
A comparison of Fig. 2(ii) and Fig. 11(ii) tells us that this truth table is same as that of OR gate.